A thesis is submitted in partial fulfillment of the requirement of Nazarbayev University for the degree of Doctor of Philosophy

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FABRICATION AND INTEGRATION OF ONE- AND TWO-DIMENSIONAL

MATERIALS FOR ADVANCED NANOSCALE DEVICES

Aidar Kemelbay

A thesis is submitted in partial fulfillment of the requirement of Nazarbayev University for the degree of Doctor of Philosophy

Supervisory committee:

Dr. Alexander Tikhonov, Nazarbayev University Dr. Marat Kaikanov, Nazarbayev University

Dr. Tevye Kuykendall, Lawrence Berkeley National Laboratory

April 2020

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Abstract

As the miniaturization of electronic circuits reach physical limits, new materials and physical phenomenon need to be exploited to further increase device density and efficiency. A number of approaches have been proposed. One of the common approaches in the scientific community is the search to understand and practically fabricate novel materials and devices at the nanoscale. In this work, we present several nanofabrication processes and unique synthetic methods that we have developed to achieve novel 1D and 2D semiconducting, dielectric, and ferroelectric materials, relevant for the integration in advanced nanoscale devices.

In particular, single-walled carbon nanotubes (CNTs) were synthesized and integrated into bottom- and top-gate field effect transistors. We demonstrated a novel CNT surface pretreatment method that enables uniform and conformal ALD coating of suspended nanotubes with various dielectric materials. Obtained all-oxide TiO₂-Al₂O₃ compound high-κ dielectric showed an improved dielectric permittivity.

Another class of semiconductor that we investigated, was transition metal dichalcogenide(TMD) layered thin film materials. We developed a novel synthetic method that we termed “lateral conversion,” which was used to grow WS₂, WSe₂, MoS₂ and MoSe₂ van der Waals materials. In this method, a metal-oxide layer is converted into TMD material using a chalcogenation reaction that propagates laterally between two inert silica layers. The method results in a multilayer structure with TMD material covered by a capping layer that protects it from the environment, contamination, and oxidation. It was shown that the technique provides control over the TMD position, shape, and thickness with sub-micron precision, at wafer scale.

A third class of materials that was studied in this work are hafnia-based ferroelectric thin films. The ability to integrate ferroelectric thin films into

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electronic devices with atomic layer deposition (ALD) has been a long-standing dream. With the discovery of ferroelectric properties in ALD hafnium oxide, the realization of some advanced architecture devices became one step closer. Here, ALD was used to synthesize Hf_0.5Zr_0.5O₂, with precisely tuned stoichiometry.

Next, the crystallization of initially amorphous Hf0.5Zr0.5O2 was performed using widely researched rapid thermal annealing (RTA), as well as by using intense pulsed ion beams (IPIBs), which was done for the first time for such application.

RTA-produced ferroelectric thin films, showed successful orthorhombic phase stabilization and annealing-temperature-dependent remnant polarization, whereas early IPIBs experiments demonstrated the ability to crystallize HfO₂, ZrO₂ and Hf_0.5Zr_0.5O₂thin films, inducing different crystallographic phases.

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Acknowledgements

This thesis is lovingly dedicated to my mother, Roza Kabenovna Mussenova.

Without her none of my achievements would have been possible.

First of all, I would like to thank my supervisors – Dr. Tevye Kuykendal, Dr.

Alexander Tikhonov and Dr. Marat Kaikanov. Dr. Tevye Kuykendal for hosting, teaching and guiding me in Berkeley for five years. Dr. Alexander Tikhonov for giving me the opportunity to work in his group and endless support in every aspect of my research and PhD life. Dr. Marat Kaikanov for introducing me to a fascinating world of accelerators. I express special appreciation to Dr. Shaul Aloni (Molecular Foundry) for his help with designing experiments and sample characterization, as well as for all the useful discussions.

I am truly grateful to the Director of the Nanofabrication Facility (Molecular Foundry) Dr. Stefano Cabrini for his support and the opportunity to work in a world-class research center. I also thank Dr. Adam Schwartzberg for his valuable insights on ALD and other fabrication techniques. It was a great pleasure to work with the Nanofabrication Facility staff, especially with Michael Elowson and Arian Gashi, from whom I learned a lot and who continuously make sure that every cleanroom user can perform high-quality research. I want to thank the Director of the Inorganic Facility (Molecular Foundry) Dr. Jeff Urban for giving me an opportunity to start my project at the Molecular Foundry. I am also grateful to Inorganic Facility staff, especially to Tracy Mattox for her help with XPS measurements and training.

My extended thanks go to Zaure táte for her love and care. I also thank my friends – Alkey Margulanuly, Arman Tuigynbek, Omar-Sayan Karabayev and Yernar Smagulov. I would particularly like to commend Arman, who supported me throughout these years. Last but not least, I am grateful to my relatives – Kozhakhmetov, Ospanov, Sabitov, Kenzheguzinov and Aliyev families.

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Financial support from the Nazarbayev University (small grant 090118FD5346) and the Ministry of Education and Science of the Republic of Kazakhstan (state-targeted program BR05236454) are acknowledged. Work at the Molecular Foundry was supported by the Office of Science, Office of Basic Energy Sciences, of the U.S.

Department of Energy under Contract No. DE-AC02-05CH11231.

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Declaration

I declare that the research contained in this thesis, unless otherwise formally indicated within the text, is the original work of the author. The thesis has not been previously submitted to this or any other university for a degree and does not incorporate any material already submitted for a degree.

Aidar Kemelbay February 22nd, 2020

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List of Abbreviations

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NC Negative Capacitance O-Phase Orthorhombic Phase

PEALD Plasma Enhanced Atomic Layer Deposition PECVD Plasma Enhanced Chemical Vapor Deposition PVD Physical Vapor Deposition

RPM Revolutions Per Minute RTA Rapid Thermal Annealing SEM Scanning Electron Microscopy SS Subthreshold Swing

SWCNT Single-Walled Carbon Nanotube TEM Transmission Electron Microscopy TMD Transition Metal Dichalcogenide WLRM White Light Reflection Microscopy XPS X-Ray Photoemission Spectroscopy XRD X-Ray Diffraction

XRR X-Ray Reflectivity

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List of Figures

2.1 Schematic illustration of MOSFET . . . 5

2.2 Chirality-dependent properties of carbon nanotubes . . . 11

2.3 Graphoepitaxial growth of carbon nanotubes on the surface of quartz 14 2.4 Transition metal dichalcogenides structure and electronic properties 18 2.5 Comparison between negative, positive and ferroelectric capacitors . 22 2.6 Ferroelectricity and structural requirements for it . . . 23

2.7 Hafnium oxide polymorphs . . . 26

2.8 Ferroelectric window of HfO₂ and its dependence on fabrication conditions . . . 27

2.9 Ferroelectric characterization of HfO₂capacitors . . . 30

3.1 CNFET fabrication process flow . . . 38

3.2 Thermal chemical vapor deposition of single-walled carbon nanotubes process diagram . . . 40

3.3 Graphoepitaxial CNTs on the surface of ST-cut quartz . . . 42

3.4 SEM images of lithographically defined electrodes . . . 43

3.5 Suspended carbon nanotube fabrication . . . 45

3.6 Morphology of thin films deposited on suspended SWCNTs . . . . 49

3.7 Raman spectroscopy of a pristine nanotube and a nanotube coated with TiO2and Al2O3 . . . 51

3.8 Chemical composition and dielectric properties of TiO2-based compound dielectric . . . 52

3.9 Electron transport properties of CNFETs . . . 54

4.1 Lithographically defined WS₂ grown using lateral conversion technique . . . 59

4.2 High-resolution Raman spectroscopy of WS₂ . . . 61

4.3 Structural characterization of WS₂ synthesized using lateral conversion . . . 63

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4.4 Lateral conversion kinetics . . . 65 4.5 The extensibility of the lateral conversion technique . . . 68 5.1 Metal Insulator Metal capacitor geometry . . . 71 5.2 XPS measurements1 of HZO samples with different HfO2-to-ZrO2

ALD cycles ratio . . . 73 5.3 X-ray reflectivity from a TiN/Hf_0.5Zr_0.5O₂/TiN multilayer stack . . 75 5.4 GIXRD measurement of annealed HZO . . . 77 5.5 Ferroelectric hysteresis measurements of Hf_0.5Zr_0.5O₂ . . . 80 5.6 SRIM simulations of protons traveling inside HfO₂/Si target . . . . 84 5.7 GIXRD measurements showing crystallization of HfO₂ after

irradiation with IPIB . . . 86 5.8 GIXRD measurements showing crystallization of ZrO₂ after

irradiation with IPIB . . . 87 5.9 GIXRD measurements showing crystallization of HfxZr1 –xO2after

irradiation with IPIB . . . 88

List of Tables

2.1 An overview of experimentally demonstrated negative capacitance field effect transistors. . . 35

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Nomenclature

ε Dielectric permittivity κ Dielectric constant µ^FE Field effect mobility ψs Surface potential ρ Electrical resistivity C Capacitance

E_c Coercive field Ig Gate leakage current I_sd Source-drain current J Beam current density

P Power

P_r Remnant polarization V_g Gate voltage

V_sd Source-drain voltage

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1. Introduction

Electronic devices have revolutionized modern society. They have had enormous impact on industry, manufacturing, information technology, healthcare, and more – pretty much every aspect our lives. We regularly carry smart phones in our pockets that would have been considered super-computers and filled a room only a few decades ago. In 1959, the invention of the metal-oxide semiconductor field effect transistor (MOSFET), and particularly later invention of the silicon-based transistor, launched a period of rapid growth in the field of electronics, with ever-increasing demands and expectations [1]. The semiconductor industry has been driven to continue delivering more and more complex and sophisticated devices by increasing the density of integrated circuits (ICs), while simultaneously decreasing their size, starting the miniaturization race. The challenges and achievements, associated with this race, can be understood by looking at two predictions that were made in 1960s-70s – Moore’s Law and Dennard scaling, which were later followed by the semiconductor industry. The former predicted that the number of transistors in integrated circuits would double every two years, whereas the latter predicted even more ambitious developments. In addition to doubling the density, circuits would become 40% faster, while the power consumption would stay constant. Currently, the state-of-the-art has been able to keep pace with the Moore’s Law, though it appears to be reaching fundamental limits within the current silicon paradigm. On the other hand, Dennard scaling has not been keeping pace since around 2006. In order to overcome existing obstacles and continue the scaling of transistors, while improving their performance and decreasing power consumption, novel materials and novel device architectures beyond silicon technology need to be developed.

A group of experts from the semiconductors industry have reviewed possible solutions in the International Technology Roadmap for Semiconductors (ITRS), which include spin FETs, negative capacitance field effect transistors (FETs), nanoelectromechanical switches and all-spin logic devices [2]. The roadmap, among materials for the next generation electronic devices, lists carbon nanotubes,

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various nanowires, III-Vs, and other materials.

The research presented here, investigates the synthesis of novel materials for next generation electronics, which includes fabrication of one- and two-dimensional semiconductors, advanced thin film high-κ dielectrics, and thin film ferroelectrics.

Novel low-dimensional semiconductors possess unique physical properties, such as ballistic conduction, high charge carrier mobility and absence of short-channel effects, making them perfectly suitable for further aggressive device miniaturization.

Together with high-κdielectrics and ferroelectrics, it becomes possible to elucidate novel phenomena, like negative capacitance, integration of which will further contribute to future electronics size and power-supply down-scaling.

Specifically, this work focuses on three materials: single-walled carbon nanotubes, transition metal dichalcogenides, and ferroelectric Hf_0.5Zr_0.5O₂. The synthesis and engineering of these materials contribute towards a common goal – the development of negative capacitance transistors and other advanced nanoscale devices.

Carbon nanotubes. We developed process flows for the synthesis of single-walled carbon nanotube (CNT) transistors, including a novel technique for atomic layer deposition (ALD) of oxides on the inert surface of defect-free nanotubes. The latter is important since ALD typically does not form continuous layers on the nanotube surfaces that are free of nucleation sites. The proposed method utilizes TiO₂-based pretreatment of CNTs, which results in nanotubes coated with a weakly interacting, continuous layer of titania. The pretreatment strategy enables subsequent ALD of high-κdielectric, does not degrade the nanotube properties (that is typically expected from the surface functionalization), and increases the dielectric permittivity of the all-oxide insulator. We believe that this technique can be extended to coat CNTs with other ALD materials, such as metals, nitrides and sulfides.

Transition metal dichalcogenides. A novel transition metal dichalcogenide (TMD) synthesis method that we call “lateral conversion” was developed, which forms a structure with TMD material sandwiched between two silica layers.

The technique is based on the chalcogenation of metal-oxide fims, and proceeds laterally between two inert layers forming 2D TMDs. The capping layer makes subsequent TMDs processing contamination-free, while it can also serve as a buffer layer for subsequent deposition of ALD thin films. ALD on pristine TMDs, similar to ALD on CNTs, is challenging due to the absence of nucleation sites on their surface; the developed technique overcomes this problem. The lateral conversion method utilizes standard lithographic approaches,

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and enables wafer-scale synthesis of TMDs with few-layer precision, and complex lithographically defined features.

Ferroelectric Hf_0.5Zr_0.5O₂. We fabricated ferroelectric thin films of Hf_0.5Zr_0.5O₂ (HZO), towards their future integration with CNTs and TMDs into negative capacitance transistors. As-synthesized HZO had an amorphous structure, so to induce the ferroelectricity, it was crystallized using two approaches: (1) conventional high-temperature annealing; and (2) a novel technique based on irradiation with intense pulsed ion beams. The former approach produced crystalline ferroelectric thin films. The latter allowed the crystallization of amorphous hafnia with an ultra-low thermal budget. We show that ion beams can controllably induce different crystallographic phases and is a promising method for producing ferroelectric HZO; ferroelectric measurements will be performed in future research.

Dissertation contents. Chapter 2 starts with a brief historical review of the state-of-the-art in the field of nanoscale metal-oxide-semiconductor (MOS) transistors, discussing their limitations and stating what needs to be done to overcome existing obstacles. Subsequent sections review some of the possibilities from two perspectives: changes that need to be made in device materials, and device architectures. CNTs and TMDs are discussed in the context of novel device materials, and their properties are reviewed. Next, ferroelectricity and the negative capacitance phenomena are introduced. Chapters 3 to 5 report the experimental details of three projects and the obtained results. Chapter 3 describes our fabrication of carbon nanotube transistors and a pretreatment process developed to uniformly cover the nanotube surface with high-κ dielectric. Chapter 4 presents the lateral conversion technique used to synthesis transition metal dichalcogenides. In chapter 5, the ALD synthesis and characterization of Hf_0.5Zr_0.5O₂are discussed. Chapter 6 summarizes the obtained results and sets goals for future research.

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2. State-of-the-art

This chapter discusses an operation principle of field effect transistors, performance requirements recognized by academia and industry, as well as future directions for transistor development.

2.1. Conventional FETs and scaling theory

Metal Oxide Field Effect Transistors (MOSFETs) were first developed in 1959 at Bell Labs by Martin Atalla and Dawon Kahng [1]. The first device was based on crystalline silicon capped with thermally grown silicon oxide. Since then, the MOSFET geometry, materials, and processes to synthesize them has significantly evolved, but the operating principle, in general, remains the same. A conventional FET consists of two highly doped regions called the source and drain connected by an oppositely and moderately doped semiconductor, which is the transistor channel (see figure 2.1). A third electrode, called the gate, is formed on top or under the channel and electrically separated from it using an insulating material. When no gate voltage is applied, the transistor can be represented as two p-n junctions connected back to back, and only leakage current can flow. If a gate voltage is applied, the semiconducting channel underneath is inverted, forming an inversion channel, which connects two highly doped regions. If source-to-drain voltage V_sd is applied, current starts flowing through the inversion channel and can be precisely modulated by changing the conductivity of the channel by applying an electric field from the gate terminal. For devices with such geometry, being able to fabricate transistors with perfect interfaces between components, ensuring good electrostatic coupling between gate and semiconducting channel, was a major obstacle. Silicon came to the rescue, due to the ability to grow oxide layers with perfect interfaces on the initial silicon substrate. The integration of thermally grown oxide lead to a reduction in the amount of surface states that screen applied electric field and deteriorates MOSFET performance. Moreover, Si can be controllably doped with

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different chemical elements that can be use to obtain all major transistor components out of a single material.

Figure 2.1. Schematic illustration of MOSFET [3].

Increasing computation complexity required more transistors to be integrated in one device. In 1960, the first IC consisting of 16 transistors was demonstrated. Since then, both industry and scientific community have invested enormous efforts to increase the density of ICs. In 1965, Gordon Moore, at the time a R&D director at Fairchild Semiconductor, predicted that the number of components in ICs would double every two years, which is today known as “Moore’s Law”. Ever-growing demand from electronics required aggressive downscaling of individual transistors in order to accommodate as many devices on as small a substrate as possible.

In addition to the size scaling, it was (and still is) required to further improve transistor performance, while reducing its power consumption. In 1974 Robert H.

Dennard formulated a goal, according to which – with each generation, transistor density should increase twice, and ICs should become 40% faster, while the power density (and power consumption) should stay constant [4]. Since then, Moore’s Law and Dennard scaling have been used to guide the industry and set the targets. Currently, Moore’s law is pushing towards its limits, and Dennard scaling was abandoned around 2006. Smaller transistors, more dense architectures, difficulties with reducing operating voltage, and higher clock speeds, have resulted in heating and short-channel effects, leakage current problems, as well as increased power consumption. As a result, new materials, new device architectures and new approaches beyond conventional MOSFET technology need to be developed for further electronics miniaturization and performance improvements. Some of the ideas, proposed toward realization of this goal, will be discussed in the next section.

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2.2. Novel low power switches

The power required for transistor operation is mostly composed of dynamic and static power. Dynamic power, required to switch a MOSFET, is proportional to the operating voltage and has the following dependence [5]:

P_dynamic=V_sd² ×I_av, (2.1)

where V_sd and Iav are source-to-drain voltage and average current, respectively.

Static power or leakage power can be calculated as follows:

P_static=V_sd×I_{o f f}, (2.2)

where I_off is the off-state leakage current. Both equations constitute total power required for transistor operation and point to the conclusion that lowering operating voltageV_sdwill lead to the reduction of total power consumption of the device.

The current flowing through the FET channel is proportional to:

I_sd ∝exp(qVg/kBT), (2.3) where k_B is the Boltzmann constant and T is the operation temperature [3]. The change in I_sd, in subthreshold region, as a function of applied gate voltage Vg is called subthreshold swing (SS) and defined as:

SS= ∂^V^g

∂^(logId), (2.4)

By combining equations 2.3 and 2.4, one can calculate that at room temperature the physical limit of SS is 60 mV/dec, which means that at least 60 mV needs to be applied to increase the current ten times. Such limitation also imposes a lower limit onV_sd and as a result the power consumption of an individual transistor.

To further investigateSS, one can extend equation 2.4 to:

SS= ∂^V^g

∂^(logId)= ∂^V^g

∂ψs

|{z}

m

∂ψs

∂^(logId)

| {z }

n

= (1+ C_s C_ins)

| {z }

m

kT q ln10

| {z }

n

, (2.5)

where ψ^s is a surface potential, C_s and C_ins are semiconductor and insulator

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capacitances, respectively. Termmis called the body factor and represents coupling between the gate and channel, whereas n governs the conduction or injection mechanism of carriers into the channel. To lower SS value, m and n should be as small as possible. Below each case will be briefly discussed and different approaches will be studied that can be taken to achieve sub-60 mV/dec operation regime.

Tunnel FET.One type of device that satisfies then < 1requirement is tunnel FET (TFET). These devices have similar structures to conventional MOSFETs, but the conduction is based on carrier tunneling. In MOSFETs, the source-drain current is modulated by changing the conductivity of semiconducting channel, whereas in TFETs, it is based on quantum tunneling of charge carriers from valence to conduction band and vice versa. One of the early experiments demonstrated this effect in Schottky barrier carbon nanotube field effect transistors (CNFETs) [6], where band-to-band tunneling was achieved by using a dual-gate configuration. One of the gate electrodes was used to electrostatically dope a nanotube and another one was used to apply a local electric field to shift the conduction and valence bands of the nanotube. Once the conduction band bendt bellow the valence band, the band-to-band tunneling could facilitate the tunneling current, increasing I_sd. This approach allowed the reduction of SS to a value as low as 40 mV/dec. However, despite delivering good switching behavior, one of the main drawbacks of TFETs is low ON current, since the amount of charge carriers is limited by the tunneling effect, which is impractical for many applications.

Impact ionization MOS. Another type of transistor, which overcomes FET limitations, is an impact ionization MOS (I-MOS) device. A typical I-MOS structure consists of p+ and n+ regions (serving as source and drain respectively) that are connected by the intrinsic region. By applying a gate voltage through the gate electrode – partially overlapping intrinsic region, it is possible to control the formed inversion layer, which can reduce the effective channel length of the transistor. When high enoughV_g is applied,V_sd starts to contribute to the electric field and increases the horizontal electric field outside the gate. At some point, the increasing vertical electrical field fromVg and the growing horizontal electric field from V_sd result in an avalanche breakdown, switching the device from the OFF to ON state, allowing charge carriers to surge into the channel, resulting in rapidI_sd growth with a very steep sub-60 mV/dec slope [7]. However, due to the close proximity of hot electrons to the oxide layer, reliability of such devices is challenging, since these electrons can be trapped, shifting the threshold voltage of

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the transistor [8]. In addition, impact ionization transistors typically require high operating voltages, which negatively impact power consumption, even though the transport characteristics have a very steep slope.

Gate coupling improvement. Both TFET and I-MOS devices can improve then term in equation 2.5, and have their own advantages and drawbacks. However, they represent a class of devices that are different from conventional MOSFETs that are predominantly used in the semiconductor industry. Many fabrication processes have been developed and studied in detail for MOSFETs by the industry and academia.

So, in this work we discuss how to improve the MOSFET performance without suggesting to replace them. As a figure of merit, theSSwill be mostly used in this work, with the aim to make it as small as possible. As previously discussed, theSS can be mathematically described with two terms -mandn(see equation 2.5). For MOSFETs the thermal factorn= (kT/q)×ln10is limited to 60 mV/dec (at room temperature), so to reduce the SS, the body factor m needs to be decreased. The body factor represents how good the electrostatic coupling between gate electrode and semiconducting channel in the FET is established. Formto be less than 1 (which will result inSS < 60 mV/dec),C_s/C_insshould have a negative value. This implies that either the semiconductor or insulator capacitance should have a negative value.

The latter can be achieved if a ferroelectric material is integrated into the gate stack of a MOSFET, since in some circumstances ferroelectric differential capacitance can become negative. This idea was first proposed as an approach to lowerSS in 2008 by Salahuddin and Data [9]. The authors suggested that this could be accomplished by integrating ferroelectric material into a FET’s gate stack. A few years later, sub-60 mV/dec operation was experimentally demonstrated in numerous devices, using various ferroelectrics and channel materials (semiconductors). Briefly, incorporation of a ferroelectric provides internal gate voltage amplification, and a ferroelectric capacitor serves as a step-up voltage transformer [9]. The work we present here is aimed to further develop the negative capacitance transistor approach, by investigating novel materials and their co-integration into devices. A more detailed overview of the negative capacitance phenomena is presented in chapter 2.4.1, whereas the next section will discuss what semiconductors can be used to improve the MOSFET performance.

2.3. 1D and 2D nanomaterials for future electronics

The low-dimensional semiconductors that will be discussed and studied in this work are carbon nanotubes and transition metal dichalcogenides. These materials

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have extraordinary mechanical, optical, thermal and chemical properties [10, 11], however, for this work we are primarily interested in utilizing their unique electronic properties in transistor applications. These alone will not significantly reduce the SS of FETs, but can help to overcome other problems, especially the short channel effects that start to dominate in conventional Si-based MOSFETs.

2.3.1 Carbon nanotubes

Carbon nanotubes are tubular structures consisting of carbon atoms arranged in a hexagonal structure with carbon-carbon bond length of 1.421 Å. This nanomaterial was first discovered in 1952 by Radushkevich et al. but did not receive proper attention until 1991 after publication by Sumlo Iijima, where double-walled and multi-walled CNTs were characterized using transmission electron microscopy [12].

Two years later, single-walled nanotubes were first reported in literature and studied [13]. Ever since, CNTs have been an ongoing subject of intense research due to their exceptional physical and chemical properties. In this work we focus on single-walled nanotubes only, so CNT will refer to single-walled CNTs, unless otherwise specified.

Chemical structure.Elemental carbon consists of a nucleus with 6 electrons around it. Two electrons occupy the1sorbital, forming theK shell and the remaining four electrons occupy the 2s and 2p orbitals, forming the L shell. In an excited state, each valence electron occupies 2s, 2px, 2py and2pz orbitals. The fourth electron excitation arises from energy released during bonding. Further, during molecular interactions, the orbitals mix into hybrid orbitals to form chemical bonds, which is called hybridization. For neighboring C atoms in graphene, one s and two p orbitals mix, resulting in so-calledsp²hybridization, oriented in the x-y plane. Such in-plane hybridization of 2s, 2px and 2py orbitals leads to the formation of three σ-bonds, responsible for chemical bonding of C atoms. These bonds define the mechanical properties of graphene that depend on the rigidity of the bond. The remaining unhybridized out-of-plane2p_z orbital is available for π-bonding; it has a small binding energy and governs the electrical properties of graphene. Thus, each carbon atom provides one electron that can be easily excited by thermal energy from valence to conduction band since they overlap. As a result, graphene is a good electrical conductor or quasi-metal.

For carbon nanotubes, which can be viewed as rolled-up graphene sheets, the situation changes significantly. Bending and curvature induction change the C-C

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bond length and angle; π-orbitals start to overlap and are no longer perpendicular toσ-orbitals. Depending on the angle used to roll up the graphene sheet, CNT can have different chirality and the nanotubes possess different physical and chemical properties.

Carbon nanotube lattice. Crystal lattices can be built by defining primitive unit cells and translational symmetry [14]. For graphene, the unit cell consists of two carbon atoms, however the crystallographic structure of CNTs is more complex (see figure 2.2). In the circumferential direction, the CNT lattice vector can be represented by a chiral vector:

C_h=na₁+ma₂, (2.6)

wherenandmare integers, together called chirality -(n,m); whereasa₁anda₂are graphene lattice vectors. In the axial direction, the CNT lattice vector is called the translation vector and can be defined as:

T =t1a₁+t2a₂, (2.7)

where t₁ and t₂ are integers. Chiral indices n and m can be used to distinguish the following types of achiral (i.e. nanotube is superimposable on its own mirror images) CNTs: (1) armchair nanotubes with (n,m = n); and (2) zigzag nanotubes with (n,m = 0). All other (n,m) CNTs are chiral. The nanotube diameter can be calculated as:

dt= |C_h| π ⁼

√C_h·C_h

π ⁼

a√

n²+nm+m²

π ^. ^(2.8)

Since chiral and translation vectors are orthogonal (i.e. perpendicular to each other), their dot product isC_h·T =0, from whicht₁andt₂can be derived:

t₁= (2m+n)/p t₂=−(2n+m)/p,

(2.9)

wherepis the greatest common divisor of(2m + n)and(2n + m). The chiral angle is the angle between the chiral vector and the primitive lattice vectora₁:

cosθ ⁼ _|^C^h^·^a¹

C_h||a₁| = 2n+m 2√

n²+nm+m². (2.10)

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The number of hexagons in one unit cell is calculated using the following equation:

N= |C_h×T|

a₁×a₂ = 2(n²+nm+m²)

p = 2|C_h|²

a²p (2.11)

Electronic properties. The electronic properties of CNTs can be derived by using the so-called zone folding scheme [15]. The first Brillouin zones of CNTs and graphene are one- and two-dimensional, respectively. The energy dispersion of graphene can be used to construct the band structure of CNTs by cutting the two-dimensional electronic dispersion relation of graphene (figure 2.2b). The number of cutting lines is equal to the number of hexagons in the unit cell of a CNT, and their length is inversely proportional to the length of the unit cell, whereas the distance between the cutting lines is inversely proportional to the diameter of CNT.

Figure 2.2. Chirality-dependent properties of carbon nanotubes. (a) Carbon nanotube chirality derivation from chiral angle, chiral and translation vectors. Reproduced from [16]

with permission from the PCCP Owner Societies. (b) Zone folding scheme used to construct band-structure of CNTs from graphene. (c) Band structure and DOS obtained for two CNTs of different chirality simulated using the “CNTbands” software [17].

Graphene does not have a band gap since the valence and conduction bands of graphene touch each other at theK point in the Brillouin zone. If the cutting line, used to obtain the band structure of CNT from graphene, passes through theKpoint, the band gap of such a nanotube will be zero and the nanotube will be metallic. If (n,m)does not allow the cutting line to pass through theKpoint, a band gap will be created resulting in a semiconducting nanotube. Figure 2.2b shows cutting lines for

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(12,0)and(13,0) zigzag nanotubes near graphene’sK point. Since the chirality of a (12,0) tube allows one of the lines to go through theK point, the tubes possess metallic properties and the opposite can be observed for semiconducting (13,0) tubes. Band structure and density of states (DOS) for both chiralities, as well as their molecular structure are presented in figure 2.2c and d. These results were obtained using “CNTbands” simulator, available at https://nanohub.org/tools/cntbands-ext/, usingP_z-orbital model [17].

Synthesis. The general approach to synthesize carbon nanomaterials is (a) via ablation of solid carbon or (b) pyrolysis of a carbon-containing gas such as ethylene or acetylene. As a result of such reactions, carbon atoms may arrange in a specific order to form fullerenes, graphene or carbon nanotubes. A possible undesirable byproduct is amorphous carbon. Since pyrolysis is a thermal decomposition process, typically requiring high processing temperatures at low pressures and good control over the rate that gasses are introduced into the reaction chamber. For carbon nanotubes, three main synthetic approaches based on ablation or pyrolysis exist: (1) arc discharge; (2) laser ablation; and (3) chemical vapor deposition (CVD).

Arc dischargeis based on the creation of an electric arc containing carbon atoms, which can be achieved by applying high voltage between two graphite electrodes at high temperatures. Typically, the resulting product is a soot containing fullerenes, nanotubes and amorphous carbon. Next, this mixture needs to be purified to remove unwanted materials and leave CNTs only. Laser ablationutilizes a laser to vaporize graphite in a high temperature reactor. The resulting carbon vapor is carried using an inert gas (e.g. Ar) and condenses onto a water-cooled collector placed downstream.

The quality and quantity of the material can be controlled by changing the laser power, reactor temperature, pressure, and catalyst nanoparticles. The latter can be used by alloying carbon targets with catalytic metals, such as Ni, Co, and their mixture.

Laser ablation and arc discharge are mostly used to synthesize large quantities of nanotubes, which can be used, for instance, to fabricate randomly oriented nanotube arrays. If additional techniques are employed, such as electrophoresis, horizontally aligned arrays can also be achieved. Both laser ablation and arc discharge require purification and very high reactor temperatures, which makes precise positioning of individual CNTs on a chip a challenging task. In this regard, chemical vapor deposition allows synthesis of nanotubes with much better control over their position on a wafer, and overall improved quality of the material.

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Chemical vapor deposition. CVD is based on introducing carbon containing gas, such as CH₄ or C₂H₂, into a preheated reactor. The growth temperature can be greatly reduced by using catalyst nanoparticles in a process called vapor-liquid-solid growth. The process starts from carbon stock decomposition and dissolution into metal nanoparticles. At a specific temperature, carbon has a limited solubility in the metal. Once the metal nanoparticle is supersaturated, the carbon nanotube starts growing by one of two mechanisms. The first one is base growth, where the catalyst nanoparticle stays attached to the substrate and the CNT grows from it; the second is tip growth, during which the catalyst nanoparticle is at the growth front and precedes the precipitation of the CNT behind it. Typical CVD synthesis temperatures range between 750 and 900^◦C. Growth processes with low thermal budget are typically required to minimize dopant redistribution in substrates; to eliminate diffusion of metal contacts that might exist on a substrate before the growth step, or to grow nanomaterials on flexible substrates, as well as in many other situations, where high temperature processing is undesirable or impossible.

CNT growth may take place “in air” or on-substrate, depending on how strong the interaction between the nanotube and substrate is. In the first case, tubes grow upwards and fall down either when the reaction has stopped or when the tube becomes too long and too heavy. To control the growth direction, high gas flow rates [18] or an electric field [19] can be used.

During on-substrate growth, CNTs can grow vertically – perpendicular to the substrate, or laterally along the substrate. Vertical CNT growth is often used to grow densely packed arrays of CNTs. For the types of devices discussed in this work, laterally grown CNTs are primarily considered. In this orientation,graphoepitaxy, crystallographic alignment with the substrate is possible. One of the first works that experimentally demonstrated this, used faceted nanosteps of sapphire that was cut at different angles with respect toc-plane [20] to guide nanotube growth in a given direction. Another graphoepitaxy example is CNT growth on single-crystalline quartz. This method was proven to promote highly horizontally aligned nanotube arrays. Figure 2.3a shows quartz crystal and different cuts that can be obtained from it, which are being used in numerous mechanical and electrical devices. ST-cut quartz shows particular utility, since on its surface, CNTs grow parallel to each other and along theX plane of the crystal. ST-cut is a type of rotated Y-cut with a cut angle of 42^◦45′. Figure 2.3d schematically shows a(5,5)single-walled nanotube on the surface of ST-cut quartz. Molecular mechanics simulations revealed that Van der Waals forces between quartz and nanotubes are responsible for the alignment, [21]

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withX direction being the most energetically favorable in terms of CNT interaction with underlying Si atoms. The largest distance between silicon atoms and nanotube is in theX direction – best seen on the right image in figure 2.3d. As a result, the interaction with CNTs is minimized. Figure 2.3b shows how the interaction energy of ST-cut quartz with the nanotube depends on the orientation angle, with a global minimum at 0 degrees, i.e. along the X direction. Interestingly, nanotubes with alignment governed by Van der Waals forces, allows them to grow perpendicular to step edges and in some situations CNTs can climb over features 3 times higher than their diameter [21].

Figure 2.3. Graphoepitaxial growth of carbon nanotubes on the surface of quartz. (a) Different quartz crystal cuts available commercially [https://www.qiaj.jp/pages/frame20/page01-e.html]. (b) Nanotube orientation dependent interaction energy between CNT and ST-cut quartz. (c) SEM image of CNTs aligned along X direction of ST-cut quartz. (d) Schematic illustration of a (5,5)CNT on the surface of ST-cut quartz in three projections. (b-d) Adapted with permission from [21]. Copyright (2019) American Chemical Society.

In addition to the ability to grow nanotubes in predefined directions, it is important to control their location on the wafer and their chirality. The former can be achieved by patterning catalyst islands from which nanotubes will grow. The latter has yet to be achieved and is the so-called“holy grail”of CNT science. Developing a process that would enable CNT growth with predefined chirality, would immediately help nanotubes to move from academia to industry. While imperfect, many different CNT growth techniques have been developed that increase the chiral selectivity, yielding predominantly semiconducting nanotubes. For instance this was achieved by controlling catalyst type [22]; introducing methanol [23] or vapors of water [24]

during the synthesis, or by selectively destroying metallic nanotubes with UV and

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other radiation [25, 26]. It is also possible to perform diameter-dependent etching [27, 28], or etching of only metallic nanotubes, which can be selectively exposed with a thermocapillary polymer [29]. Another method is to burn metallic nanotubes using electrical breakdown after integration into devices by applying source-drain voltage only [30] or both source-drain and gate voltages [31].

While synthesis of single-chirality nanotubes is still challenging, it is at least possible to control the diameter distribution of CNTs. This can be done by growing them from catalyst nanoparticles of known size. Low diameter nanoparticles (below ~2 nm) define nanotube diameter and can be used to synthesize almost exclusively single-walled nanotubes. In addition to diameter control, nanoparticles density can control the density of nanotubes. Thus, growing CNTs on quartz, from lithographically defined catalyst islands with nanoparticles of known size, allows control of their growth direction, location on the wafer, and diameter distribution, respectively. This, among other issues, is still not enough to end the silicon hegemony, but sufficient for fundamental studies.

Carbon nanotube field effect transistors (CNFETs). A typical CNFET device consists of a CNT that is clamped with metallic pads from both sides, serving as source and drain electrodes. Gate electrodes can be located in close proximity to the nanotube and separated from it with dielectric. The nanotube itself plays the role of the semiconducting channel, hence the requirement of growing purely semiconducting tubes, discussed previously. CNFETs are objects of intense research due to several compelling electrical properties of CNTs: ballistic electron transport (i.e. without scattering with defects, phonons, etc.) over micrometers range [32, 33];

high field effect (>79’000 cm²/Vs) and intrinsic (>100’000 cm²/Vs) [34] mobilities at room temperature; high current densities, and absence of short-channel effect in devices as small as 9 nm [35].

Many different CNFET geometries exist and can be divided into two categories:

transistors with nanotubes (1) on-substrate or (2) suspended. Devices with on-substrate nanotubes are easier to fabricate, but they typically suffer from unwanted interactions with the underlying substrate. Fixed oxide trapped charges can screen electric fields from the gate electrode, and shift threshold voltage of the transistor as a result. Another undesirable interaction is the interaction with water molecules present on the surface of the substrate. This may result in hysteretic behavior (i.e. forward and backward gate voltage sweeps have different threshold voltages), which is unacceptable for many practical FET applications, but can be

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used to fabricate memory devices [36]. Higher quality oxides and/or passivation layers can be engineered to overcome the above-mentioned problems. Typically, this is realized by fabricating top-gated devices using high-κ dielectrics such as HfO₂, Al₂O₃and others. In addition to a higher quality interface with the nanotube, top gated devices allow switching of individual transistors in ICs, unlike common bottom gate devices.

In contrast to on-substrate devices, nanotubes suspended in air may offer an unaltered conduction (in terms of nanotube-substrate interaction) with hysteresis-free performance [37]. Most suspended devices are fabricated with a bottom gate, which decreases the efficiency of the electric field due to the low dielectric permittivity of air and/or relatively high distance from the nanotube.

Another drawback of such a device is its fragility due to the suspension of a-few-atoms-thick nanomaterial at its “heart”. However, one of the most important advantages of suspended nanotube configuration is the ability to integrate a gate electrode around the nanotube. Such configuration is typically called a gate-all-around (GAA) geometry, which is natural to CNTs, and provides the best electrostatic coupling between the semiconducting channel and the gate. By integrating the GAA structure with the incorporation of a thin, high-k dielectric, it should be possible to achieve ideal near-60 mV/dec SS switching behavior.

Although the ideal limit has not yet been demonstrated experimentally,SSreaching a close-to-perfect 99 mV/dec operation has been shown [38].

In terms of conduction mechanism, two types of CNFETs exist: ohmic and Schottky barrier transistors. If the charge carriers can travel through the metal - nanotube (semiconductor) junction freely, the contact is called ohmic and the electron transport depends on the nanotube properties, i.e. the gate electrode changes the conductivity of the CNT only. If charge carriers should undergo injection into the channel through the barrier formed at the interface between semiconductor (CNT) and metallic electrode, the device is called a Schottky barrier CNFET (sb-CNFET).

In this case, an electric field is needed to lower the barrier and channel resistance to turn on the transistor. With decreasing CNT channel lengths, the Schottky barrier starts to dominate and the metal-to-nanotube junction becomes more important for the conduction mechanism.

Carbon nanotubes are ambipolar in nature (i.e. can conduct both electrons and holes at positive and negative gate voltages respectively), however, in real-world devices, the contact material typically defines the polarity of sb-CNFET due to Fermi level

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mismatch. If a high work function metal is used for the electrodes, such as Au or Pd, the CNFET will be p-type [39]; and if a low work function metal is used, such as Sc or Er, the CNFET will be n-type [40]. Another approach to control the polarity of the CNTFET, is to engineer an environment around it. For instance, it was shown that non-stoichiometric HfO2 deposited on single-walled CNT bundles, results in n-type doping [41], despite using high-work function Pt source/drain electrodes. In addition to conductivity control, CNT passivation eliminates its interaction with the ambient environment, reducing the device-to-device variability.

2.3.2 Transition metal dichalcogenides

Transition metal dichalcogenides (TMDs) are another class of materials having extraordinary physical and chemical properties and are finding more and more applications in electronic and optical devices. TMD materials have a chemical formula of ME₂, where M is a transition metal, such as Mo, W, Pt or Pd; and E is one of the chalcogen atoms from group 16 of the periodic table, such as S, Se or Te.

The structure and properties of TMDs are discussed in the following section.

Structure. TMDs may have different structures, but two of the most stable ones typically observed are octahedral 1T and trigonal prismatic 2H phases (figure 2.4a).

The former has “ABC” stacking of atoms, whereas the latter has “ABA”. In the 2H phase, chalcogen atoms are located in the same position in each layer of the stacked material, which is in contrast to the 1T phase, where chalcogen atoms are at an angle with regards to their “relatives” in the previous/next atomic plane.

Due to a wide variety of possible transition metal - dichalcogenide combinations, a lot of new materials have been predicted and experimentally shown, with many unique and tunable properties. Figure 2.4b shows different TMD materials, among which MoS2is one of the most studied materials with promising characteristics for electronic devices. Similar to graphene, many TMDs have two-dimensional (2D) layered structures, and have desirable quantum confined properties when isolated as few- to single-layers. Further, most of the monolayer TMDs are inherently semiconducting and no additional band gap engineering is typically required, unless specific properties need tailoring.

Electronic properties. Figure 2.4c shows how the band structure of MoS₂ varies with the number of layers. Monolayer MoS2 is a direct band gap semiconductor with a theoretical band gap of 1.7 eV [42]. Thicker MoS2 becomes an indirect band gap semiconductor and loses some of its compelling properties, such as

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strong photoluminescence, important for optoelectronic applications [43]. Another MoS₂ property that emerges only in monolayer material is the valley polarization phenomena, which arises due to inversion symmetry breaking and spin-orbit coupling [44]. Figure 2.4d schematically shows monolayer 2H MoS₂band structure.

Other TMDs also show thickness-dependent properties. For instance, the band gap of WS2changes from direct to indirect and increases with growing number of layers, while for Pt-based dichalcogenides, it is only indirect [45].

Figure 2.4. Transition metal dichalcogenides structure and electronic properties. (a) Octahedral and trigonal phases of TMDs. (b) A family of TMD materials having different physical properties. (c) Layer-dependent band structure of 2H MoS2. (d) Schematic illustration of a monolayer 2H MoS₂band structure. Reprinted by permission from Springer Nature [46]: Journal Publisher - Nature, Nature Reviews Materials © 2017.

Screening length. Besides leakage current and power dissipation problems, aggressive miniaturization of electronics leads to appearance of short-channel effects. One of the ways to quantitatively evaluate them is to estimate the screening length of FETs, using the following equation:

λ ⁼

(εbody

ε^ox ^×^W^DM^×^t^ox )1/2

, (2.12)

where εbody and εox are dielectric permittivities of semiconducting channel and dielectric (oxide), respectively.W_DMis maximum doping dependent depletion width andt_oxis dielectric thickness [47]. Once the channel widthl_cbecomes comparable

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with the screening lengthλ, charge carrier concentration starts to be more controlled by the drain electrode, rather than by the gate voltage. In general, for successful MOSFET down-scalingl_c should be ~2 times larger thanλ. For 2D TMDs,W_DM becomes equal to the thickness of the material, so a low screening length can be obtained by using a-few-atoms-thick TMDs with high-κdielectric thin films.

Synthesis. The first scientific study of TMDs, particularly MoS₂, dates back to 1923. In this work [48] the authors characterized the crystal structure of molybdenite using X-ray diffraction, and were able to study the arrangement of atoms in the crystal. After 40+ years of work, by 1970, about 60 TMDs were discovered,

~20 of them having layered structures [49]. However, the rapid resurgence in interest in TMDs resumed some 40 years later, after the well-known experimental demonstration of graphene. Mechanical exfoliation of graphene, TMDs, and other materials became a hot topic since the technique enabled the synthesis of high-quality monolayers on scales sufficient for fundamental studies [11, 50, 51].

Chemical exfoliation is another way of producing mono- and a few-layer TMDs [52, 53]. This is typically achieved by ultrasonication of TMD powder in an appropriate solvent. Intercalation with different atoms can be used to facilitate the process, which may require additional purification steps, otherwise intercalated material can cause phase changes, converting the semiconducting 2H phase into the metallic 1T phase [54].

The main drawback of any exfoliation approach is associated with the difficulty of scaling up the process. Precise, wafer-scale fabrication is still challenging using this method. Thus, bottom-up approaches need to be explored to make TMD fabrication compatible with very large scale integration (VLSI), which is also applicable to other nanomaterials and systems. Currently, chemical vapor deposition (CVD) is a prevalent method for large area growth of TMDs. This can be achieved by introducing transition metal and chalcogen vapors in the reactor, which can form TMDs on the substrate surface. One of the most cost-effective and widely used techniques for synthesizing TMDs involves the direct vaporization of sulfur and transition metal containing powders by heating. The vapors are carried by inert gas (e.g. Ar or N2), forming TMDs on a substrate located downstream inside the reactor, or above a boat containing the transition metal powder [55]. Metal organic chemical vapor deposition (MOCVD) has also been used to synthesize high quality wafer-scale MoS₂using gas phase precursors [56]. The resulting material had a high electron mobility of 30 cm²V^-1s^-1 at room temperature and was uniform across a 4 inch wafer.

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Another related method is atomic layer deposition (ALD) [57]. In the referenced example, gas phase Mo(CO)₆ and H₂S were used to produce MoS₂. Additional high-temperature annealing in H₂S atmosphere was required to improve the material’s properties and stoichiometry. One of the problems with ALD of sulfides is that it requires dedicated reactor, as sulfur can cause contamination of the reactor and other materials that will be grown in the same chamber.

Yet another approach is to pre-deposit a thin film seed-layer of metal (M) [58] or metal oxide (MO_x) [59, 60], which can be later chalcogenated. This approach allows precise control over the location of the future TMD material, since the seed layer can be lithographically patterned by performing lift-off or dry/wet etching. Metals or metal oxides can be deposited using physical vapor deposition (PVD) processes, such as electron beam and thermal evaporation, or sputtering. PVD typically allows uniform thin film deposition with a thickness of 5+ nm and a precision of ~1 nm.

As a result, the final material is 5±1 nm or thicker. After conversion, depending on the seed layer and chalcogen type, the final thickness of the TMD is even higher, resulting in a multilayer or bulk material. Thus, for monolayer and a few layer TMDs, the seed layer should be super-thin and for reproducible results, run-to-run thickness reproducibility should be sub-1 nm. Atomic layer deposition (ALD)is a perfect solution to meet the imposed seed layer thickness requirement, since it allows angstrom-level precision growth of (mostly) oxides on a wafer scale. In addition, ALD can uniformly and conformally cover high aspect ratio structures, which may enable 3D integration of TMDs into devices. ALD was used to grow WO3 of different thickness ranging from 1 to 3 nm, resulting in a uniform and pinhole-free thin film on the surface of 4 inch wafer. It was shown that by changing thickness and converting the resulting oxide into sulfide, it is possible to control the number of layers in WS₂and achieve monolayer material [61].

2.4. Ferroelectricity and negative capacitance

Introducing the negative capacitance (NC) FET concept requires revisiting the equation 2.5 that estimates the slope of the FET transfer curve. Two conclusions were made: terms m and n, which are body factor and conduction/injection mechanisms respectively, need to be minimized to achieve steep slope performance.

Since NCFETs are still FETs,n is limited to 60 mV/dec (at room temperature), so

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the subthreshold swing of a FET can be rewritten as:

SS= ∂^V^g

∂^(logId)= ∂^V^g

∂ψs

|{z}

m

×60mV/dec. (2.13)

Thus, for FET’s sub-Boltzmann operation m should be less than 1. A possible solution for that lies in the utilization of a material with negative capacitance in the FET gate stack. In the next section, NC phenomena, and what materials can deliver it, will be discussed and reviewed.

2.4.1 Negative capacitance

A typical FET gate stack is a multilayer structure, consisting of a gate electrode and a semiconducting channel, separated with an insulator. This configuration can be treated as two capacitors connected in series, among which gate voltageV_g is divided. The ratio between the gate voltageV_gand the potential at the surface of the channelψ, from equation 2.13 can be calculated using the following equation:

∂^Vg

∂ψs

=1+ Cs

C_ins. (2.14)

IfC_inswill be negative, themterm in equation 2.14 will become less than 1 and it will be possible to achieve sub-60 mV/dec operation. To demonstrate the behavior of a regular (positive) or a negative capacitors, the following relationship can be used:

C=dQ

dV, (2.15)

which means that forCto be negative, the amount of charge should decrease, while increasing the applied voltage (figure 2.5a). Capacitance can also be explained from the potential energy point of view:

C= (d²U

dQ² )−1

. (2.16)

Figure 2.5b compares energy landscapes of a positive and negative capacitors. One

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class of materials that can obtain negative capacitance values are ferroelectrics.

Ferroelectric materials possess spontaneous polarization, which can be reversed by applying an electric field. Ferroelectric capacitors show a complex energy landscape, depicted in figure 2.5c, and unlike regular dielectric material, with a quadratic relation between energy and charge, ferroelectrics have two energy minima. From the Q-U relationship around Q = 0 (denoted with dashed rectangle), we can see that the curvature is oriented downwards, confirming that the ferroelectric material has a region that can have a negative capacitance (compare with the energy landscape of a negative capacitor in figure 2.5b). To demonstrate the microscopic origin of ferroelectric material polarization, figure 2.6a shows the unit cell of a ferroelectric orthorhombic phase of HfO₂. Two polarization states are demonstrated, where oxygen atoms displace depending on the direction of the applied field.

Figure 2.5. Comparison between negative, positive and ferroelectric capacitors. (a) Voltage-charge characteristics. Energy landscape of (b) positive and negative, as well as (c) ferroelectric capacitors. The region under the red box in (c) signifies negative capacitance region.

Landau theory of phase transitions [62] shows that the free energy U = U(P)of a ferroelectric can be represented using the following dependence:

U =α^P²⁺β^P⁴⁺γ^P⁶−EP, (2.17) where α^, β ând γ are material dependent coefficients, out of which β ând γ âre temperature independent. Coefficientα can be further written as:

α ⁼^a⁰^(T−T_C), (2.18)

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wherea₀is a temperature independent quantity, T is the temperature andT_C is the Curie temperature. When T_C >T, α becomes negative, which gives the negative curvature to the energy landscape of a ferroelectric material (region under red box in figure 2.5c).

The equilibrium position can be determined by finding the extremum ofU: dU

dP =0, (2.19)

which, by combining with equation 2.17. will result in:

E=2α^P⁺⁴β^P³⁺⁶γ^P⁵^. ^(2.20) This equation represents the dependence between the external electric field and the polarizability of ferroelectric. Figure 2.6b shows the polarization-voltage characteristic of hafnium oxide, a ferroelectric that can be represented by this equation. The point where the hysteresis loop intersects with the Y-axis is the remnant polarization P_r of the ferroelectric, whereas the intersection with X-axis gives the coercive fieldE_c, required to switch the polarization.

Figure 2.6. Ferroelectricity and structural requirements for it. (a) Two metastable polarization states of hafnium oxide unit cell. Reproduced from the Royal Society of Chemistry [63]. (b) Typical ferroelectric hysteresis loop of doped hafnium oxide sample fabricated in this work. (c) Crystallographic families review and the ferroelectric properties.

By combining equations 2.16, 2.17 and 2.18, considering that for ferroelectricsQ = P[9], one can obtain the following equation for capacitance atP = 0:

C= 1 2α ⁼

1

2a₀(T−T_C). (2.21)

A thesis is submitted in partial fulfillment of the requirement of Nazarbayev University for the degree of Doctor of Philosophy

FABRICATION AND INTEGRATION OF ONE- AND TWO-DIMENSIONAL

MATERIALS FOR ADVANCED NANOSCALE DEVICES

Aidar Kemelbay

A thesis is submitted in partial fulfillment of the requirement of Nazarbayev University for the degree of Doctor of Philosophy

Supervisory committee:

Dr. Alexander Tikhonov, Nazarbayev University Dr. Marat Kaikanov, Nazarbayev University

Dr. Tevye Kuykendall, Lawrence Berkeley National Laboratory

April 2020

Abstract

Acknowledgements

Declaration

Contents

List of Abbreviations

List of Figures

List of Tables

Nomenclature

1. Introduction

2. State-of-the-art

2.1. Conventional FETs and scaling theory

2.2. Novel low power switches

2.3. 1D and 2D nanomaterials for future electronics

2.3.1 Carbon nanotubes

2.3.2 Transition metal dichalcogenides

2.4. Ferroelectricity and negative capacitance

2.4.1 Negative capacitance