Various structural principles for the construction of memory devices are described in the third part of the manual. Similarly, if there is an XOR element at one of the inputs (control input), the signal at its other input (information input) passes through.
Typical combination nodes
We consider the operation of the device according to the order of data recording in table 1.7. The change in the state of this trigger in accordance with the level of the information signal (D) is carried out by the positive edge (edge) of the control signal (C), which is indicated by the corresponding sign in the graphic designation (as well as in the table).
Serial carry adder
It remains only to wait for the display of the required number code and write it in the corresponding data receiver. The selection of the register for recording data is carried out by changing the state of the switch R by pressing the corresponding key. The device in question has two modes of operation determined by the state of the switch D: the mode of entering input data (D = 1) and the mode of applying the summary of prepared data (D = 0).
The direction of the strobe signals to the corresponding blocks is carried out by the AND elements installed in the corresponding parts of the circuit.
Summing-subtracting device
The corresponding recording gate is formed by the Res block, built according to the scheme in figure 1.4, e.g. The need to convert the number code into an additional code also arises in the event of a negative result. In this case, the corresponding conversion is performed in the sign block, in which the negative sign of the result is also set.
Adder for sequential operands
Appropriate indicators allow visual observation of the step-by-step process of bit summation.
Serial adder in automatic mode
Read (or write) time - the interval between the moments of the control signal (read / write) and the completion of the corresponding operation. By the nature of the RAM memory elements, they are divided into static (SRAM, static RAM) and dynamic (DRAM, dynamic RAM). In the 2D structure (figure 3.1), the m-bit memory cells (MC, Memory Cells) are connected to the corresponding outputs of the decoder, i.e.
The corresponding elements of the columns (bits) are connected by a vertical line - the internal data line (bit line, write / read line).
ROM type memory elements
In MOS transistors corresponding to zero storage, the thickness of the gate oxide increases, which leads to an increase in the threshold voltage of the transistor. In this case, the operating voltage of the system is not able to open the transistor. Elimination of part of the jumpers is characteristic of the charger with fusible jumpers (Figure 3.6, a).
As memory elements in memory devices of the EPROM and EEPROM types, transistors of the MNOP ((Metal, Nitride, Oxide, Semiconductor)) and LIZMOS (the addition of LIZ to the MOS designation derives from the words Charge Avalanche) types used, the operation of which is based on the construction of floating gates [1].
Structural principles of microprocessor systems
The diode explodes with the formation of a short circuit in it and plays the role of the conductive jumper that appears. In reprogrammable memory devices of the EPROM and EEPROM types, it is possible to erase old information and replace it with new information as a result of a special process for which the memory device is removed from the operating mode. Along with this, control signals coordinate the operation of the processor (master, master) with the operation of memory or input / output devices (slave, slave).
To connect input / output devices (I / O) or external devices (IU) to the system bus, their signals must comply with the standards of the respective interfaces through which communication is carried out.
Intel 8085 microprocessor
Five signs are indicated: Z (Zero) - zero result, C (Carry) - word division, AC (Auxiliary Carry) - auxiliary word division, S (Sign) - sign, P (Parity) - word parity. In this case, the state of the command counter is automatically stored on the stack. INTA (Interrupt Acknowledge) - vectored interrupt acknowledge strobe output after completion of the current command cycle.
This is a response to the HOLD signal generated at the end of the current machine cycle.
Intel 8085 Microprocessor Command System
The generalized address bits of registers that are data sources are expressed by letters S (Data Source), registers that are receivers of data, letters D (Data Destination), pairs of registers with letters. P (pair). By substituting certain addresses instead of alphabetic characters, we get the codes of specific variants of the command. The comparison operation is performed by subtracting the operands and setting the sign of the result (Z and S).
In the third column, a hyphen means that the execution of the command is not accompanied by the development of flag flags, the plus sign indicates the installation of all characters, the plus sign in parentheses indicates the installation of all characters except.
Addressing Methods
Label - the symbolic address of the command to which a transition takes place in the program. If there are two operands in the command, the first is the data receiver and the second is the source. Then we present several program structures with different sizes (bytes) and the method of addressing commands, which will allow us to evaluate the presented program structure and determine the advantages and disadvantages of the commands used in it.
The structure of the simulator, the organization of work with it and its functional capabilities (working with various tools in its composition) will be taken into consideration when studying the relevant programs.
Data forwarding
Enter the first command of the program below by moving the cursor to the tabular distance (eg by pressing the Tab key) and press Enter. Similarly, when you specify the addresses of the following ports as 02, 03, and 04, set them to OUT; open the memory window by selecting Tools / Memory Editor in the main simulator window;. In the Cumulative Sum block, the sum of the values of the members of the arithmetic progression recorded in the memory in the previous block of the program is.
The Serial Subtraction and Direct Subtraction blocks perform the process of sequential subtraction of the data used for summation from the previously obtained sum value.
Double Byte Arithmetic
The program presented in this section is devoted to the study of the principles of organizing work with subprograms. In each of the blocks Mul1 and Mul2, data for multiplication is entered and the multiplication subroutine (MUL) is called, and then the display subroutine (PER) is called. The program presented in this section is devoted to the study of the principles of binary-decimal conversion.
The hexadecimal values of the converted numbers and the results of the corresponding conversion are displayed in the allocated memory cells.
Organization of work with interruptions
The material in this section is intended to examine the possibility of practical implementation of the general principles of building a microprocessor system on the example of developing a model of such a system with an original command system. The model was developed in the ElectronicsWorkbench [2] circuit modeling software, designed for the modeling and analysis of electrical circuits. The proposed model allows students to get a complete picture of the structural principles of building a microprocessor system, a system of its teams, and acquire initial skills in the development of such systems.
To ensure the greatest simplicity of the model and the visibility of its function, it was intended to work with 4-bit data (notebooks) and built on the basis of general principles of construction of a microprocessor system.
MP4M Model Structure
You can also leave its content unchanged, which will be described in the description of the system's operating modes. After retrieving the code of the current command and storing it in the command register, its content is incremented. According to the command code, the command decoder (DC_16) includes the appropriate firmware to control the execution of the current command, i.e.
A combination firmware device (Combi, Combi-national Circuit) generates spatial and temporal control signals that guarantee the execution of the current command.
Modes of Operation and Command System Model MP4M
A timer (CLK) determines the timing of control signals transmitted to devices involved in command execution. The input device is based on encoders, the inputs of which are connected to the corresponding keys. The system's memory consists of two subunits of 16 cells, one of which is used to store command codes as part of the system's work program, and the other is used to store data involved in operations performed in the program and information necessary for the program's work (for example, organization of cyclical program structures).
The memory control unit (MCon, Memory Control) enables the selection of one of the memory units (code or data) and its mode of operation (input, write, read) according to the control signals received from the input device or from the microprocessor.
ADS 8 A←(A)±[(C)]; TC
Examples of organization of work of the MP4M model
To illustrate the capabilities of the model, we provide descriptions of two programs for organizing its work. The program presented below is intended to add data in the cells of the data block of the memory system of the model in question (in cells 1-5 in the above program). After the completion of this program, the value of the least significant row of the addition result is displayed in the indicators of register A (number C), and the value of the higher order is determined by briefly pressing the Space key (number 3).
The original structure of the considered model, consisting of the multivariation of its modes of operation and its multivariate system of commands, offers possibilities for composing different types of programs for the system and contributes to the development of the creative abilities of its users.
